发明授权
US5930651A Method of forming a semiconductor device having a plurality of cavity
defined gating regions
失效
形成具有多个空腔限定的门控区域的半导体器件的方法
- 专利标题： Method of forming a semiconductor device having a plurality of cavity defined gating regions
- 专利标题（中）： 形成具有多个空腔限定的门控区域的半导体器件的方法
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申请号： US814787申请日： 1997-03-10
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公开(公告)号： US5930651A公开(公告)日： 1999-07-27
- 发明人: Yoshio Terasawa
- 申请人： Yoshio Terasawa
- 申请人地址： JPX
- 专利权人： NGK Insulators, Ltd.
- 当前专利权人： NGK Insulators, Ltd.
- 当前专利权人地址： JPX
- 优先权： JPX6-92478 19940428
- 主分类号： H01L21/329
- IPC分类号： H01L21/329 ; H01L29/06 ; H01L29/739 ; H01L21/30 ; H01L21/46
摘要：
A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrates are joined to each other by heating them at 800.degree. C. in a hydrogen atmosphere.
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