Invention Grant
US5933147A Computer graphics memory architecture which processes a full pixel of 3D
color and z value data in a single I/O transaction
失效
计算机图形存储器架构,可在单个I / O事务中处理3D颜色和z值数据的完整像素
- Patent Title: Computer graphics memory architecture which processes a full pixel of 3D color and z value data in a single I/O transaction
- Patent Title (中): 计算机图形存储器架构,可在单个I / O事务中处理3D颜色和z值数据的完整像素
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Application No.: US531600Application Date: 1995-09-21
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Publication No.: US5933147APublication Date: 1999-08-03
- Inventor: Bao-Tyan Wang , Wei-Kuo Chia , Jin-Han Hsiao
- Applicant: Bao-Tyan Wang , Wei-Kuo Chia , Jin-Han Hsiao
- Applicant Address: TWX Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TWX Hsinchu
- Main IPC: G06T15/00
- IPC: G06T15/00

Abstract:
An improved computer graphics memory architecture has a frame buffer and a Z buffer, each having a forward and reverse part, each of which is wide enough to handle two pixels of data. A data path is connected to the buffers so that in a 3-D application, a full pixel of both color and Z-value data is transported along the data path in a single I/O transaction. In a 2-D application, two pixels of data are transported along the data path in a single I/O transaction. In a preferred embodiment, both the frame and Z buffers are divided into two parts each wide enough to handle one pixel of data part. In 3-D applications, a data path is selectively connected to the buffers in a manner so that one pixel of color data and one pixel of Z-value data are simultaneously transported to the drawing processor during each I/O transaction. In this preferred embodiment, a first reversing switch such as a multiplexer circuit, is provided to reverse data that arrives from the buffer in reverse order. A second reversing switch, such as a multiplexer circuit, is provided to return the data to the proper buffer after processing. In a preferred embodiment for 2-D applications, two pixels of data are transported to the drawing processor each I/O transaction. In this preferred embodiment, a third reversing switch is provided to reverse data that arrives from the buffer in reverse order. A fourth reversing switch is provided to return the data to the proper buffer after processing.
Public/Granted literature
- US5093791A Variable gain synchrophasing Public/Granted day:1992-03-03
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |