发明授权
- 专利标题: Prioritizing the repair of faults in a semiconductor memory device
- 专利标题(中): 对半导体存储器件中的故障进行优先排序
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申请号: US122426申请日: 1998-07-24
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公开(公告)号: US5940335A公开(公告)日: 1999-08-17
- 发明人: Toshiaki Kirihata
- 申请人: Toshiaki Kirihata
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G11C29/04
- IPC分类号: G11C29/04 ; G11C29/00 ; G11C7/00
摘要:
A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each of which encompasses a plurality of redundancy elements. The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.
公开/授权文献
- US5508438A Phosphorus compounds 公开/授权日:1996-04-16
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