发明授权
US5940706A Process for preventing misalignment in split-gate flash memory cell
失效
用于防止分闸式闪存单元中的未对准的过程
- 专利标题: Process for preventing misalignment in split-gate flash memory cell
- 专利标题(中): 用于防止分闸式闪存单元中的未对准的过程
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申请号: US988764申请日: 1997-12-11
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公开(公告)号: US5940706A公开(公告)日: 1999-08-17
- 发明人: Hung-Cheng Sung , Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh
- 申请人: Hung-Cheng Sung , Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh
- 申请人地址: TWX Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd
- 当前专利权人地址: TWX Hsin-Chu
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L29/423 ; H01L21/8247
摘要:
A select transistor for flash memory cells is made by the following steps. Over the blanket second dielectric layer, and an oxynitride layer form a channel mask for patterning the drain and floating gate. Etch the oxynitride layer through the mask to form a channel alignment mask down to a silicon nitride layer with a drain region opening and a floating gate opening. Etch the floating gate opening through the second dielectric layer. Form a polyoxide region in the floating gate layer at the bottom of the floating gate opening by reacting the exposed portion of the floating gate layer with a reactant. Form a drain region in the substrate. Etch away the oxynitride layer and the silicon nitride layer. Pattern the floating gate electrode by etching away the floating gate layer except below the polyoxide region. Form an interelectrode dielectric layer and a second gate electrode layer over the drain region and a portion of the polyoxide region. Form a source region in the substrate self-aligned with the polyoxide region.
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