It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.