Invention Grant
US5943505A System for high speed data and command transfer over an interface where a non-maskable interrupt signal indicates either a write command or received data 失效
用于通过不可屏蔽中断信号指示写命令或接收数据的接口进行高速数据和命令传输的系统

System for high speed data and command transfer over an interface where
a non-maskable interrupt signal indicates either a write command or
received data
Abstract:
The apparatus and method for high speed data and command transfer over an interface (202), such as an ISA or PCMCIA bus or interface, includes a transceiver (206) and a processor (210) having a direct memory access (DMA) controller (240), a memory (211) for storage of data, and a channel interface (218) for connection to a communications channel. The processor (210) is responsive through a set of program instructions, such as software or firmware, to receive an interrupt signal (310, 315) and, when the interrupt signal indicates a write command (320, 330), to transfer data via the transceiver from the interface to the memory for transmission over the communications channel (335), and when the interrupt signal indicates data received from the communications channel (350), the processor further responsive to generate a read command and transfer data from the memory to the interface via the transceiver (355).
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