发明授权
- 专利标题: Air gap spacer formation for high performance MOSFETs
- 专利标题(中): 用于高性能MOSFET的气隙间隔物形成
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申请号: US175193申请日: 1998-10-20
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公开(公告)号: US5959337A公开(公告)日: 1999-09-28
- 发明人: Mark I. Gardner , Daniel Kadosh , Michael P. Duane
- 申请人: Mark I. Gardner , Daniel Kadosh , Michael P. Duane
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L29/78 ; H07L29/78
摘要:
A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate. An interlevel dielectric is deposited to a level above the gate conductor across the semiconductor topography such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the gate conductor, and the interlevel dielectric is planarized to a level substantially coplanar with an upper surface of the masking structure. In an alternative embodiment, a refractory metal is deposited across an upper surface of the masking structure and across the source/drain implant areas subsequent to forming said source/drain implant areas. The refractory metal is heated to form a metal silicide overlying the source/drain implant areas and residual refractory metal is removed from above the masking structure. In yet another alternative embodiment, a single high-energy ion implant is used to simultaneously form the source/drain implant area and the lightly doped drain implant area following removal of select portions of the gate conductors.