A non-volatile semiconductor memory device comprises a bit line 402, a plurality of word lines 401 arranged to cross the bit line 402, a plurality of non-volatile memory cells 404 which are disposed at the crossing points of the bit line 402 and the word lines 401 and which have a drain 404a connected to the bit line 402 and a control gate 404f connected to the corresponding word line 401, anda word line potential applying means 300, 500 wherein in an ordinary reading mode, a selective potential is applied to a word line 401 selected from the plurality of word lines, while a non-selective potential, which is lower than the selective potential, is applied to unselected word lines 401 in response to an address signal, and in a prescribed mode, the selective potential is applied to a word line 401 selected from the plurality of word lines, while a prescribed potential, which is lower than the non-selective potential, is applied to the unselected word lines in response to an address signal.