发明授权
- 专利标题: Semiconductor memory device
- 专利标题(中): 半导体存储器件
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申请号: US982457申请日: 1997-12-02
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公开(公告)号: US5963467A公开(公告)日: 1999-10-05
- 发明人: Shinichi Miyatake , Shigekazu Kase , Masayuki Nakamura , Masatoshi Hasegawa , Kazuhiko Kajigaya
- 申请人: Shinichi Miyatake , Shigekazu Kase , Masayuki Nakamura , Masatoshi Hasegawa , Kazuhiko Kajigaya
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX8-336444 19961202
- 主分类号: G11C14/00
- IPC分类号: G11C14/00 ; G11C11/22 ; G11C11/407 ; H01L21/822 ; H01L21/8242 ; H01L21/8246 ; H01L27/04 ; H01L27/105 ; H01L27/108 ; G11C11/24
摘要:
In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by indirectly detecting that the plate voltage has reached a predetermined potential near a intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging of the pair of bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.