A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a column of floating gates on the dielectric; (3) forming an inhibit mask adjacent a first side of the column of floating gates; (4) implanting a dopant adjacent the first side and a second side of the column of floating gates, the first dopant having a second conductivity type opposite the first conductivity type; (5) forming a thermal oxide adjacent the first and second side of the column of floating gates such that the dopant adjacent the first side of the column is separated from the floating gates by the dielectric and the dopant adjacent the second side of the column is separated from the floating gates by a bird's beak encroachment of the thermal oxide formation; and (6) completing formation of control gate dielectric and control gates.