The first circuit inputs a clock signal from MICON. The second circuit inputs a clock signal corresponding to the clock signal from the first circuit, and outputs a judgment signal continued for a specified time from the time when the clock signal is inputted. The judgment signal is inputted to the third circuit. A standby signal from MICON is inputted to the third circuit. When MICON is normal, the clock signal properly outputted, and to the AND circuit, the second signal is inputted, and if the standby signal is inputted from MICON with the second signal inputted, it can be judged that the standby signal is properly outputted from the normal MICON. Consequently, when both judgment signal and standby signal are inputted, the third circuit outputs the standby active signal to the first circuit.