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US5983254A Zero-latency pipeline architecture for digital filters 失效
数字滤波器的零延迟流水线架构

Zero-latency pipeline architecture for digital filters
Abstract:
In a digital filter, data is received through an input path, and data in the filter is transported to an output through an output path. At least one delay element is disposed on the input path, and at least another delay element is disposed on the output path. The specific positions of the delay elements on the respective paths are selected to yield an optimal combination of filter parameters including the maximum computation delay, cost, and power consumption of the filter.
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