Invention Grant
- Patent Title: Zero-latency pipeline architecture for digital filters
- Patent Title (中): 数字滤波器的零延迟流水线架构
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Application No.: US713687Application Date: 1996-09-17
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Publication No.: US5983254APublication Date: 1999-11-09
- Inventor: Kameran Azadet
- Applicant: Kameran Azadet
- Applicant Address: NJ Murray Hill
- Assignee: Lucent Technologies Inc.
- Current Assignee: Lucent Technologies Inc.
- Current Assignee Address: NJ Murray Hill
- Main IPC: H03H17/02
- IPC: H03H17/02 ; H03H17/04 ; H03H17/06 ; G06F17/10
Abstract:
In a digital filter, data is received through an input path, and data in the filter is transported to an output through an output path. At least one delay element is disposed on the input path, and at least another delay element is disposed on the output path. The specific positions of the delay elements on the respective paths are selected to yield an optimal combination of filter parameters including the maximum computation delay, cost, and power consumption of the filter.
Public/Granted literature
- US5178685A Method for forming solar cell contacts and interconnecting solar cells Public/Granted day:1993-01-12
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