发明授权
US6016315A Virtual contiguous FIFO for combining multiple data packets into a
single contiguous stream
失效
用于将多个数据分组组合成单个连续流的虚拟连续FIFO
- 专利标题: Virtual contiguous FIFO for combining multiple data packets into a single contiguous stream
- 专利标题(中): 用于将多个数据分组组合成单个连续流的虚拟连续FIFO
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申请号: US846294申请日: 1997-04-30
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公开(公告)号: US6016315A公开(公告)日: 2000-01-18
- 发明人: Peter Chambers , Scott E. Harrow
- 申请人: Peter Chambers , Scott E. Harrow
- 申请人地址: CA San Jose
- 专利权人: VLSI Technology, Inc.
- 当前专利权人: VLSI Technology, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: H04L12/56
- IPC分类号: H04L12/56 ; H04L12/50
摘要:
A virtual contiguous system for combining multiple and arbitrarily-sized and aligned digital data packets from a PCI bus to a DSP circuit is disclosed. Information from the PCI bus is supplied directly to a plurality of FIFO RAM memory units. Each packet of digital data includes data packet descriptors identifying at least the start address for each data packet and the size of each data packet. The system utilizes this information to operate a read pointer and a write pointer to remove data from the FIFO RAM memory units on a sequential bit-by-bit basis and to supply said data packets to said RAM memory units by means of a write pointer operated by said control circuit. The information transfer is managed on the read side of the FIFO RAM memory units with minimal processing on the write side.
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