A clock compensation circuit includes a clock tree; a reference clock; a phase detector for detecting relative phase information of the tree clock and the reference clock; a controller, coupled to said phase detector, for determining and controlling the amount of delay necessary to shift the output of the clock tree in phase with the reference clock; and a programmable delay logic coupled to said controller. The programmable delay logic comprises a string of delay elements that selectively participate in a delay string for shifting the tree clock in phase with the reference clock.