发明授权
US6023567A Method and apparatus for verifying timing rules for an integrated
circuit design
失效
用于验证集成电路设计的时序规则的方法和装置
- 专利标题： Method and apparatus for verifying timing rules for an integrated circuit design
- 专利标题（中）： 用于验证集成电路设计的时序规则的方法和装置
-
申请号： US726589申请日： 1996-10-07
-
公开(公告)号： US6023567A公开(公告)日： 2000-02-08
- 发明人: Peter James Osler , Tad Jeffrey Wilder , Charles Barry Winn
- 申请人： Peter James Osler , Tad Jeffrey Wilder , Charles Barry Winn
- 申请人地址： NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： NY Armonk
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.
公开/授权文献
- US5213449A Apparatus for inserting wick drains into the earth 公开/授权日：1993-05-25
信息查询
