发明授权
US6027964A Method of making an IGFET with a selectively doped gate in combination
with a protected resistor
失效
制造具有选择性掺杂栅极的IGFET与保护电阻器组合的方法
- 专利标题: Method of making an IGFET with a selectively doped gate in combination with a protected resistor
- 专利标题(中): 制造具有选择性掺杂栅极的IGFET与保护电阻器组合的方法
-
申请号: US905681申请日: 1997-08-04
-
公开(公告)号: US6027964A公开(公告)日: 2000-02-22
- 发明人: Mark I. Gardner , Daniel Kadosh , Michael Duane
- 申请人: Mark I. Gardner , Daniel Kadosh , Michael Duane
- 申请人地址: CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: CA Sunnyvale
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L21/266 ; H01L21/336 ; H01L27/06 ; H01L21/8234
摘要:
A method of making an IGFET with a selectively doped gate in combination with a protected resistor includes the steps of providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the active region and the resistor region, forming a masking layer over the insulating layer that includes an opening above a first portion of the gate and covers the resistor region and a second portion of the gate, applying an etch using the masking layer as an etch mask to remove the insulating layer above the first portion of the gate so that an unetched portion of the insulating layer forms a gate-protect insulator over the second portion of the gate and another unetched portion of the insulating layer forms a resistor-protect insulator over the diffused resistor, and forming a source and a drain in the active region including at least partially doping the source and the drain during a doping step that provides more doping for the first portion of the gate than for the second portion of the gate after forming the masking layer. In this manner, the masking layer can provide both an etch mask for the resistor-protect insulator and an implant mask for selectively doping the gate.
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