A high speed memory cell current measurement circuit uses an on-chip reference current circuit that generates a reference current Iref. The reference current circuit includes a first current source transistor. An on-chip current comparison circuit has a second current source transistor that is coupled to the first current source transistor so as to mirror the reference current Iref at a fixed current ratio WR. The current comparison circuit has a current connection path connecting the second current source transistor to a memory cell in the semiconductor memory device whose current is to be compared with Iref/WR. The memory cell is selected from the cells in a memory array using the device's on-chip address decoder circuitry. An on-chip result generation subcircuit, coupled to the current connection path between the second current source transistor and the memory cell, produces a Result signal that indicates whether current flowing through the memory cell is more or less than Iref/WR. In one mode of operation the on-chip reference current circuit is coupled to an on-chip connection pad suitable for connection to an external current source that determines the reference current. In another mode of operation the on-chip reference current circuit is coupled to a dummy memory cell. In this mode the reference current is determined by current drawn by the dummy memory cell. The voltage applied to the dummy memory cell's gate can be externally controlled, thereby allowing external control of the amount of the dummy memory cell's current.