Invention Grant
- Patent Title: Method of fabricating dual voltage MOS transistors
- Patent Title (中): 制造双电压MOS晶体管的方法
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Application No.: US108107Application Date: 1998-06-30
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Publication No.: US6033958APublication Date: 2000-03-07
- Inventor: Jih-Wen Chou , Cheng-Han Huang
- Applicant: Jih-Wen Chou , Cheng-Han Huang
- Applicant Address: TWX Hsin-Chu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TWX Hsin-Chu
- Priority: TWX87105530 19980413
- Main IPC: H01L21/8234
- IPC: H01L21/8234
Abstract:
A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.
Public/Granted literature
- USD426628S Combined natural sound reproduction and aroma dispensing device Public/Granted day:2000-06-13
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