发明授权
US6043692A Circuit and method for generating clock signals with an incrementally
reduced effective frequency
失效
用于产生具有逐渐减小的有效频率的时钟信号的电路和方法
- 专利标题: Circuit and method for generating clock signals with an incrementally reduced effective frequency
- 专利标题(中): 用于产生具有逐渐减小的有效频率的时钟信号的电路和方法
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申请号: US114380申请日: 1998-07-13
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公开(公告)号: US6043692A公开(公告)日: 2000-03-28
- 发明人: Joseph D. Linoff
- 申请人: Joseph D. Linoff
- 申请人地址: CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: H03K23/66
- IPC分类号: H03K23/66 ; H03B19/00
摘要:
The present invention provides a novel clock frequency divider that accepts an input clock having an input clock frequency and provides an output clock with an effective clock frequency of one of 1/N, 2/N, . . . , (N-1)/N, N/N times the input clock frequency, where N is an integer. The clock frequency divider of the present invention divides the input clock frequency asymmetrically by filtering out one or more of each N pulses on the input clock, as dictated by select signals. For example, in a clock frequency divider having N=8, a first clock output signal filters out one of each eight pulses, retaining seven pulses. Therefore, the effective frequency of the output clock signal is (N-1)/N, or 7/8, times the frequency of input clock signal. Similarly, a second output clock signal retains six of every eight pulses, a third retains five, and so forth.