发明授权
US6044012A Non-volatile memory array using gate breakdown structure in standard sub
0.35 micron CMOS process
有权
非易失性存储器阵列采用栅极击穿结构,在标准sub 0.35微米CMOS工艺中
- 专利标题: Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process
- 专利标题(中): 非易失性存储器阵列采用栅极击穿结构,在标准sub 0.35微米CMOS工艺中
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申请号: US263375申请日: 1999-03-05
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公开(公告)号: US6044012A公开(公告)日: 2000-03-28
- 发明人: Kameswara K. Rao , Martin L. Voogel , Shahin Toutounchi , James Karp
- 申请人: Kameswara K. Rao , Martin L. Voogel , Shahin Toutounchi , James Karp
- 申请人地址: CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: G11C17/16
- IPC分类号: G11C17/16 ; G11C11/34
摘要:
A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process. The state of the low voltage storage transistor can be read through the p-channel transistor, or through a dedicated high voltage n-channel transistor. In one embodiment, the programming voltage is generated by a charge pump circuit fabricated in accordance with a standard sub 0.35 micron process. In another embodiment, the decoder circuits that access the non-volatile memory cell use high voltage p-channel transistors to transmit the high programming voltage. Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.
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