In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a succeeding stage. At least one of the pipeline stages includes a means for recirculating an output from the pipeline stage as an input to the pipeline stage for a predetermined number of times before passing the output to a succeeding stage. The predetermined number of times represents a clock period that includes more than one assertion of a clock signal. With such an arrangement, a circuit which performs a process, such as multiplication and division, in accordance with a particular bandwidth requirement requires less hardware than in other circuits performing the same process. The foregoing arrangement provides a flexible approach which can be adapted for particular bandwidth requirements and constraints which vary with each particular application and system in which such a process is performed.