发明授权
- 专利标题: Memory cell
- 专利标题(中): 存储单元
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申请号: US105724申请日: 1998-06-26
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公开(公告)号: US6055177A公开(公告)日: 2000-04-25
- 发明人: Pidugu L. Narayana , Daniel E. Cress , Andrew L. Hawkins , Derrick Savage
- 申请人: Pidugu L. Narayana , Daniel E. Cress , Andrew L. Hawkins , Derrick Savage
- 申请人地址: CA San Jose
- 专利权人: Cypress Semiconductor Corp.
- 当前专利权人: Cypress Semiconductor Corp.
- 当前专利权人地址: CA San Jose
- 主分类号: G11C8/16
- IPC分类号: G11C8/16 ; G11C11/00
摘要:
A circuit that may be used as a memory cell that may be capable of a differential write and a single ended read. The circuit generally comprises a memory storage element having a write bitline, a complement write bitline and a read bitline. One or more first gates may be configured to pass data on the write bitline and the inverted write bitline during a write operation. The write operation may occur in response to a write control signal. A second gate may be configured to pass data on from the storage element to the read bitline in response to read control signal. As a result, the circuit may be written by both the write bitline and the complement write bitline and may be read by the read bitline.
公开/授权文献
- USD412241S Portion of a shoe upper 公开/授权日:1999-07-27