发明授权
US6055199A Test circuit for a semiconductor memory device and method for burn-in
test
有权
一种用于半导体存储器件的测试电路和用于老化测试的方法
- 专利标题: Test circuit for a semiconductor memory device and method for burn-in test
- 专利标题(中): 一种用于半导体存储器件的测试电路和用于老化测试的方法
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申请号: US176880申请日: 1998-10-21
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公开(公告)号: US6055199A公开(公告)日: 2000-04-25
- 发明人: Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
- 申请人: Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 主分类号: G11C29/50
- IPC分类号: G11C29/50 ; G11C7/00
摘要:
A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.
公开/授权文献
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