发明授权
- 专利标题: Clock signal detection circuit
- 专利标题(中): 时钟信号检测电路
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申请号: US89508申请日: 1998-06-03
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公开(公告)号: US6065129A公开(公告)日: 2000-05-16
- 发明人: Hisaya Sakamoto , Akihiko Sugata , Tetsuya Kiyonaga , Akimitsu Miyazaki
- 申请人: Hisaya Sakamoto , Akihiko Sugata , Tetsuya Kiyonaga , Akimitsu Miyazaki
- 申请人地址: JPX Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX10-003686 19980112
- 主分类号: H04B10/40
- IPC分类号: H04B10/40 ; H03K5/19 ; H04B10/00 ; H04B10/50 ; H04B10/60 ; H04L7/027 ; H04L25/02 ; H04L25/03 ; G06F1/04
摘要:
A clock signal detection circuit includes a diode to which a clock signal is applied as an input. If a voltage VD IN on the anode side of the diode is greater than a voltage VD OUT on the cathode side, the clock signal is fed into a transmission line and arrives at a reflecting load upon elapse of a prescribed delay time. When the voltage VD IN on the anode side of the diode becomes smaller than the voltage VD OUT on the cathode side, the clock signal is reflected by the reflecting load and returns to the cathode of the diode through the transmission line. This introduction and reflection of the clock signal is repeated at the clock signal period so that the amplitude on the output side of the diode is enlarged, thereby making it possible to obtain, from an averaging circuit, a clock detection voltage substantially equal to the amplitude value of the clock signal.
公开/授权文献
- USD426206S Command workstation image for a computer display 公开/授权日:2000-06-06