发明授权
- 专利标题: Voltage output circuit and image display device
- 专利标题(中): 电压输出电路和图像显示装置
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申请号: US712644申请日: 1996-09-11
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公开(公告)号: US6067066A公开(公告)日: 2000-05-23
- 发明人: Yasushi Kubota , Osamu Sasaki , Hiroshi Yoneda
- 申请人: Yasushi Kubota , Osamu Sasaki , Hiroshi Yoneda
- 申请人地址: JPX Osaka
- 专利权人: Sharp Kabushiki Kaisha
- 当前专利权人: Sharp Kabushiki Kaisha
- 当前专利权人地址: JPX Osaka
- 优先权: JPX7-261898 19951009; JPX8-013287 19960129; JPX8-066941 19960322
- 主分类号: G09G3/20
- IPC分类号: G09G3/20 ; G09G3/36
摘要:
A voltage output circuit has decoders, a selecting circuit, a logical circuit and an output circuit in order to select one of plural gradation power source lines for a prescribed period based upon k bits and m bits of an n-bit digital signal. The k bits of the digital signal are converting into 2.sup.k decoded signals by one decoder, and another m bits are converted into 2.sup.m decoded signals by the other decoder. The selecting circuit generates a signal for selecting one of periods which were obtained by dividing one horizontal scanning period into 2.sup.k based upon k-numbered timing signals by using the 2.sup.k decoded signals. The logical circuit generates 2.sup.n signals composed of combinations of the signals from the selecting circuit and the 2.sup.m decoded signals. Moreover, one of the 2.sup.m gradation power source lines is selected by an output switch by using the signal from the logical circuit. As a result, in an image display device using a digital signal as an input video signal, a number of gradation power source lines is reduced and the arrangement of driving circuits is simplified without deteriorating display quality. As a result, a cost of the image display device can be lowered.
公开/授权文献
- USD344826S Mop 公开/授权日:1994-03-01
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