发明授权
- 专利标题: Static semiconductor memory device operating at high speed under lower power supply voltage
- 专利标题(中): 静态半导体存储器件在较低电源电压下高速工作
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申请号: US72138申请日: 1998-05-05
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公开(公告)号: US6067256A公开(公告)日: 2000-05-23
- 发明人: Masayuki Yamashita , Hideki Kawamura
- 申请人: Masayuki Yamashita , Hideki Kawamura
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 主分类号: G11C7/12
- IPC分类号: G11C7/12 ; G11C11/419 ; G11C16/04
摘要:
A bit line load element for reducing a bit line amplitude during data reading is formed of p- and n-channel MOS transistors connected in parallel. When a word line is driven to the selected state, the p-channel MOS transistor is held off. In the data write operation, both the n- and p-channel MOS transistors are turned off. Even under a low power supply voltage, a sufficiently large bit line amplitude can be produced without an influence by a size of the bit line load element. By deactivating the bit line load element in the data write operation, it is possible to prevent generation of a DC current during data writing.
公开/授权文献
- USD391751S Bladder for a shoe sole 公开/授权日:1998-03-10
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