发明授权
- 专利标题: Circuit for use in a Viterbi decoder
- 专利标题(中): 用于维特比解码器的电路
-
申请号: US62685申请日: 1998-04-20
-
公开(公告)号: US06070263A公开(公告)日: 2000-05-30
- 发明人: Chi-ying Tsui , Roger Shu Kwan Cheng
- 申请人: Chi-ying Tsui , Roger Shu Kwan Cheng
- 申请人地址: IL Schaumburg
- 专利权人: Motorola, Inc.
- 当前专利权人: Motorola, Inc.
- 当前专利权人地址: IL Schaumburg
- 主分类号: H03M13/41
- IPC分类号: H03M13/41 ; G06F11/10
摘要:
A circuit for use in the add-compare-select circuit of a Viterbi decoder to determine the maximum likelihood path through states in a coding trellis uses a modified butterfly structure. Selection registers select between branch metric values at time i and partial path metric values at time i-1 in dependence on comparisons of branch metric difference values at time i and partial path metric difference values at time i-1. The selected values are added to provide new partial path metric at time i. The circuit provides a significant reduction in power consumption and area over conventional designs.
公开/授权文献
- USD391425S Headboard unit 公开/授权日:1998-03-03