发明授权
US6075418A System with downstream set or clear for measuring signal propagation
delays on integrated circuits
有权
具有下行设置或清除功能的系统用于测量集成电路上的信号传播延迟
- 专利标题: System with downstream set or clear for measuring signal propagation delays on integrated circuits
- 专利标题(中): 具有下行设置或清除功能的系统用于测量集成电路上的信号传播延迟
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申请号: US235419申请日: 1999-01-20
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公开(公告)号: US6075418A公开(公告)日: 2000-06-13
- 发明人: Christopher H. Kingsley , Robert W. Wells , Robert D. Patrie
- 申请人: Christopher H. Kingsley , Robert W. Wells , Robert D. Patrie
- 申请人地址: CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: G01R31/30
- IPC分类号: G01R31/30 ; G01R31/317 ; G01R31/3185 ; G01R31/3193 ; G04F10/02 ; H03B5/02
摘要:
A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.