发明授权
- 专利标题: Electrostatic discharge protection bus/die edge seal
- 专利标题(中): 静电放电保护总线/模具边缘密封
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申请号: US116434申请日: 1998-07-15
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公开(公告)号: US6078068A公开(公告)日: 2000-06-20
- 发明人: Ronald Kazuo Tamura
- 申请人: Ronald Kazuo Tamura
- 申请人地址: CA Milpitas
- 专利权人: Adaptec, Inc.
- 当前专利权人: Adaptec, Inc.
- 当前专利权人地址: CA Milpitas
- 主分类号: H01L23/62
- IPC分类号: H01L23/62 ; H01L27/02 ; H01L27/118 ; H01L27/10
摘要:
Disclosed is an integrated circuit chip having an improved ESD protection structure. The integrated circuit chip includes a core logic region having a plurality of transistor devices that are interconnected to form a specific integrated circuit device. A plurality of input/output cells are defined along a periphery of the integrated circuit chip. An ESD bus die edge seal that defines a single ring around the periphery of the integrated circuit chip is provided. The ESD bus die edge seal is positioned outside of the plurality of input/output cells closest to a physical outer edge of the integrated circuit chip. Further, a plurality of (Vss) supply cells are contained in selected ones of the plurality of input/output cells. And, a plurality of ESD cross-coupled diodes are connected between the plurality of (Vss) supply cells and the ESD bus die edge seal. Advantageously, this combined ESD bus and die edge seal provides a more compact structure that also has more uniform charged contaminant collection characteristics.
公开/授权文献
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