A ferroelectric layer having a low dielectric constant which is used for a ferroelectric memory element is provided. Also, the ferroelectric layer having a high melting point used for the ferroelectric memory element is provided. An FET 20 has a stacked structure including a gate oxidation layer 24, a floating gate 26, a ferroelectric layer 28, and a control gate 30 deposited on a channel region CH in that order, the channel region CH being formed in a semiconductor substrate 22 made of silicon. The ferroelectric layer 28 consists of a thin film made of a mixed crystal composed of Sr.sub.2 (Ta.sub.1-x Nb.sub.x).sub.2 O.sub.7. The crystal structure of both Sr.sub.2 Nb.sub.2 O.sub.7 and Sr.sub.2 Ta.sub.2 O.sub.7 is pyramid quadratic structure, and their lattice constants are similar to each other. Their relative dielectric constants are low, and their melting points are high. Curie temperature related with their ferroelectricity is, however, too high in Sr.sub.2 Nb.sub.2 O.sub.7 and too low in Sr.sub.2 Ta.sub.2 O.sub.7. In order to overcome the discrepancies, the ferroelectric layer 28 having desired curie temperature is formed with a mixed crystal made of Sr.sub.2 (Ta.sub.1-x Nbx).sub.2 O.sub.7.