发明授权
- 专利标题： Circuit apparatus for evaluating the data content of memory cells
- 专利标题（中）： 用于评估存储器单元的数据内容的电路装置
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申请号： US133704申请日： 1998-08-13
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公开(公告)号： US6097650A公开(公告)日： 2000-08-01
- 发明人: Rudiger Brede , Dominique Savignac
- 申请人： Rudiger Brede , Dominique Savignac
- 申请人地址： DEX Munich
- 专利权人： Siemens Aktiengesellschaft
- 当前专利权人： Siemens Aktiengesellschaft
- 当前专利权人地址： DEX Munich
- 优先权： DEX19735137 19970813
- 主分类号： G11C11/409
- IPC分类号： G11C11/409 ; G11C7/06 ; G11C11/4091 ; G11C11/4094 ; G11C7/00
摘要：
A circuit apparatus for evaluating a data content of memory cells of an integrated semiconductor memory, which memory cells are disposed along bit lines and word lines. The circuit apparatus has a voltage compensation device with voltage compensation elements which are connected for the purpose of voltage coupling of in each case two neighboring bit lines and which enable compensation for a capacitive coupling between the bit lines.
公开/授权文献
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