发明授权
- 专利标题: Output circuit, pulse width modulating circuit and semiconductor integrated circuit in which the level of ringing is reduced
- 专利标题(中): 输出电路,脉宽调制电路和半导体集成电路,其中振铃电平降低
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申请号: US215298申请日: 1998-12-18
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公开(公告)号: US6100729A公开(公告)日: 2000-08-08
- 发明人: Hideo Nagano , Yasufumi Chujo
- 申请人: Hideo Nagano , Yasufumi Chujo
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX10-077856 19980325
- 主分类号: H03K5/04
- IPC分类号: H03K5/04 ; H03K5/02 ; H03K17/16 ; H03K3/00
摘要:
An output circuit is constructed such that a load capacitor is not charged by an external power supply but by a first charge storage element within a semiconductor chip that is charged before the load capacitor. The charge stored in the load capacitor is released not directly to the ground but to a second charge storage element within the semiconductor chip and discharged before discharging of the load capacitor.
公开/授权文献
- US4357687A Adaptive word line pull down 公开/授权日:1982-11-02
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