DRAM with column slices improves circuit redundancy. Slices have global column length, and memory is divided in groups with size of redundancy columns having slices. Failure detected among slices of corresponding storage is replaced by corresponding redundancy column slice, such that column redundancy division is in vertical column direction. Column includes global data line shared by column slices and multiple blocks. Redundant column is added to memory array, and redundant control circuits or comparator are proximate to data sense amplifiers. Defective column address are provided to controller through non-volatile memory, or laser-blown or electrically-programmable fuses. When column address is presented, incoming address is compared with stored address, such that select data is output on redundant data line when equal addresses (i.e., hit detect), or normal data is output when unequal addresses (i.e., "miss" detected).