发明授权
US6115757A DMA control apparatus for multi-byte serial-bit transfer in a
predetermined byte pattern and between memories associated with
different asynchronously operating processors for a distributed system
失效
用于以预定字节模式进行多字节串行比特传输的DMA控制装置，以及与用于分布式系统的不同异步操作处理器相关联的存储器之间的DMA控制装置
- 专利标题： DMA control apparatus for multi-byte serial-bit transfer in a predetermined byte pattern and between memories associated with different asynchronously operating processors for a distributed system
- 专利标题（中）： 用于以预定字节模式进行多字节串行比特传输的DMA控制装置，以及与用于分布式系统的不同异步操作处理器相关联的存储器之间的DMA控制装置
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申请号： US833005申请日： 1997-04-04
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公开(公告)号： US6115757A公开(公告)日： 2000-09-05
- 发明人: Takayoshi Honda
- 申请人： Takayoshi Honda
- 申请人地址： JPX Kariya
- 专利权人： Denso Corporation
- 当前专利权人： Denso Corporation
- 当前专利权人地址： JPX Kariya
- 优先权： JPX8-086483 19960409
- 主分类号： G06F13/28
- IPC分类号： G06F13/28 ; G06F13/00 ; G06F11/00 ; G06F12/00 ; G06F13/40
摘要：
A DMA control apparatus transfers a data set of bytes, with no intermixing these data bytes and with favorable efficiency. A DMA controller receives data bytes serially and writes this data to a RAM. At this time, when the serially sent data are taken to be made up of data sets where one information item is formed of two bytes, the DMA controller, while temporarily storing data received in odd-numbered order in a data-set adjusting register, controls block write of this together with data received in even-numbered order to the RAM. Due to this, access where data other than these data sets is intermixed is eliminated, even in a case where asynchronous word-unit access of the RAM is performed by the CPU.
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