The invention is directed to a process for forming p+ and n+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected hobo a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is selectively performed in the portion of the metal silicide layer overlying a field oxide region that separates the n-type region from the p-type region in the substrate surface. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.