发明授权
US6124609A Split gate flash memory with buried source to shrink cell dimension and
increase coupling ratio
有权
具有埋地源的分流式闪存，以收缩电池尺寸并增加耦合比
- 专利标题： Split gate flash memory with buried source to shrink cell dimension and increase coupling ratio
- 专利标题（中）： 具有埋地源的分流式闪存，以收缩电池尺寸并增加耦合比
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申请号： US439369申请日： 1999-11-15
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公开(公告)号： US6124609A公开(公告)日： 2000-09-26
- 发明人: Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
- 申请人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
- 申请人地址： TWX Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co.
- 当前专利权人地址： TWX Hsin-Chu
- 主分类号： H01L21/8247
- IPC分类号： H01L21/8247 ; H01L27/115 ; H01L29/788
摘要：
A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.
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