One aspect of the invention is a shared signal processor comprising input circuitry to receive a plurality of input signals and output circuitry operable to transmit a plurality of output signals. Storage circuitry is operable to store state information and signal data for each of the plurality of input signals and output signals. A state machine is coupled to the input circuitry, output circuitry, and storage circuitry and is operable to poll each input signal and output signal to identify a first signal requiring processing. The state machine is further operable to load the state information and signal data associated with the first signal and process the first signal.