A circuit (12) for symbol decision directed feedback synchronization includes a current synchonization clock (45) that provides an initial sampling point and selects a detector corresponding to a current symbol decision. The circuit further includes a plurality of detectors (31, 32, 33, and 34) including the detector corresponding to the current symbol decision, a buffer (736) for storing the output of the detector corresponding to the current symbol decision and a processor (300) for seeking within a predetermined window about the initial sampling point for an optimum phase value to provide an adjustment signal which is used by the processor to adjust a subsequent symbol's sychronization clock to provide an optimal sampling point.