发明授权
- 专利标题: Method of fabricating CMOS semiconductor device
- 专利标题(中): 制造CMOS半导体器件的方法
-
申请号: US382698申请日: 1999-08-25
-
公开(公告)号: US6133082A公开(公告)日: 2000-10-17
- 发明人: Sadaaki Masuoka
- 申请人: Sadaaki Masuoka
- 申请人地址: JPX Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX10-242848 19980828
- 主分类号: H01L29/78
- IPC分类号: H01L29/78 ; H01L21/265 ; H01L21/336 ; H01L21/8238 ; H01L27/092
摘要:
A method of fabricating a CMOS semiconductor device is provided, which decreases the number of necessary photolithography processes for forming the LDD and pocket structures. A first pair of doped regions of a first conductivity type are formed in a first section of a semiconductor substrate and a second pair of doped regions of the first conductivity type are formed in a second section thereof. Then, a third pair of doped regions of a second conductivity type are formed in the first pair of doped regions and a fourth pair of doped regions of the second conductivity type are formed in the second pair of doped regions. Thereafter, an impurity of the second conductivity type is selectively ion-implanted into the first section while covering the second section with a mask, thereby forming a fifth pair of doped regions of the second conductivity type from the first pair of remaining doped regions. Further, another impurity of the first conductivity type is selectively ion-implanted into the first section while the second section is covered with the mask, thereby forming a sixth pair of doped regions of the first conductivity type from the second pair of doped regions. The channeling effect of an implanted impurity may be utilized, where a pair of doped regions in one of the first and second sections are formed deeper than another pair of doped regions in the other.
公开/授权文献
- US5598757A Method for shearing panels 公开/授权日:1997-02-04
信息查询
IPC分类: