发明授权
US06134155A Synchronized circuit for coordinating address pointers across clock
domains
有权
用于协调跨时钟域的地址指针的同步电路
- 专利标题： Synchronized circuit for coordinating address pointers across clock domains
- 专利标题（中）： 用于协调跨时钟域的地址指针的同步电路
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申请号： US407156申请日： 1999-09-28
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公开(公告)号： US06134155A公开(公告)日： 2000-10-17
- 发明人: Sheung-Fan Wen
- 申请人： Sheung-Fan Wen
- 申请人地址： CA Santa Clara
- 专利权人： National Semiconductor Corporation
- 当前专利权人： National Semiconductor Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： G11C7/00
- IPC分类号： G11C7/00 ; G06F5/10 ; G06F5/12 ; G11C7/10
摘要：
A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.