Invention Grant
US6144081A Method to suppress subthreshold leakage due to sharp isolation corners
in submicron FET structures
失效
抑制由亚微米FET结构中的尖锐隔离角引起的亚阈值泄漏的方法
- Patent Title: Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures
- Patent Title (中): 抑制由亚微米FET结构中的尖锐隔离角引起的亚阈值泄漏的方法
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Application No.: US540961Application Date: 1995-10-11
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Publication No.: US6144081APublication Date: 2000-11-07
- Inventor: Louis Lu-Chen Hsu , Chang-Ming Hsieh , Lyndon Ronald Logan , Jack Allan Mandelman , Seiki Ogura
- Applicant: Louis Lu-Chen Hsu , Chang-Ming Hsieh , Lyndon Ronald Logan , Jack Allan Mandelman , Seiki Ogura
- Applicant Address: NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: NY Armonk
- Main IPC: G03F1/08
- IPC: G03F1/08 ; H01L21/027 ; H01L21/28 ; H01L21/336 ; H01L21/76 ; H01L29/423 ; H01L29/78 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113

Abstract:
A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.
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