A nonvolatile memory circuit that includes a load circuit coupled to a band-gap reference circuit and a nonvolatile memory cell. The load line circuit is configured to provide a programming voltage to the nonvolatile memory cell. The programming voltage may be generated in response to the reference voltage generated by the band-gap reference circuit. The nonvolatile memory circuit may also include an amplifying circuit that amplifies the reference voltage of the band-gap circuit, and provides the amplified reference voltage to the load circuit. The nonvolatile memory circuit may further include a voltage trim circuit that trims the amplified reference voltage and provides the trimmed amplified reference voltage to the load circuit. The reference voltage, amplified reference voltage, and the trimmed amplified reference voltage may each output a stable voltage that is independent of variations in process parameters, operating temperatures, and supply voltages of the nonvolatile memory circuit.