发明授权
US6148357A Integrated CPU and memory controller utilizing a communication link
having isochronous and asynchronous priority modes
失效
使用具有等时和异步优先模式的通信链路的集成CPU和存储器控制器
- 专利标题： Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
- 专利标题（中）： 使用具有等时和异步优先模式的通信链路的集成CPU和存储器控制器
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申请号： US99228申请日： 1998-06-17
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公开(公告)号： US6148357A公开(公告)日： 2000-11-14
- 发明人: Dale E. Gulick , Larry D. Hewitt
- 申请人： Dale E. Gulick , Larry D. Hewitt
- 申请人地址： CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： CA Sunnyvale
- 主分类号： G06F13/40
- IPC分类号： G06F13/40 ; G06F13/38
摘要：
An integrated circuit includes a central processing unit, a memory controller circuit for interfacing to system memory, and an interconnect bus controller for interfacing to an interconnect bus. The interconnect bus controller gives priority to transfer of asynchronous data during a first transfer mode and priority to transfer of isochronous data during a second transfer mode. A switch selectively couples the CPU, the memory controller circuit and the interconnect bus controller.
公开/授权文献
- USD419982S Computer bezel 公开/授权日：2000-02-01
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