发明授权
US6157992A Synchronous semiconductor memory having read data mask controlled output
circuit
失效
具有读取数据掩模控制输出电路的同步半导体存储器
- 专利标题: Synchronous semiconductor memory having read data mask controlled output circuit
- 专利标题(中): 具有读取数据掩模控制输出电路的同步半导体存储器
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申请号: US768089申请日: 1996-12-16
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公开(公告)号: US6157992A公开(公告)日: 2000-12-05
- 发明人: Seiji Sawada , Yasuhiro Konishi
- 申请人: Seiji Sawada , Yasuhiro Konishi
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-330394 19951219
- 主分类号: G11C11/407
- IPC分类号: G11C11/407 ; G11C7/00 ; G11C7/10 ; G11C11/401 ; G11C11/409 ; G06F12/00
摘要:
A read enable signal OEMF activated in response to an input command is applied to an N minus 2 clock shift circuit included in an output control circuit for implementation of ZCAS latency. An output signal of the N minus 2 clock shift circuit and an internal mask instructing signal activated in response to an external mask instructing signal are logically processed and applied to a one-clock shift circuit. According to an output signal OEMQM of one-clock shift circuit, a data output enable signal OEM controlling activation/inactivation of an output buffer circuit is activated/inactivated. Data output controlling portion occupying area of a synchronous dynamic random access memory is reduced and timings of activation/inactivation of data output by different commands are made the same.
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