发明授权
- 专利标题: Hardware multiplication of scaled integers
- 专利标题(中): 缩放整数的硬件乘法
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申请号: US186965申请日: 1998-11-05
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公开(公告)号: US6161119A公开(公告)日: 2000-12-12
- 发明人: Steven Allen Gabriel , James F. Blinn
- 申请人: Steven Allen Gabriel , James F. Blinn
- 申请人地址: WA Redmond
- 专利权人: Microsoft Corporation
- 当前专利权人: Microsoft Corporation
- 当前专利权人地址: WA Redmond
- 主分类号: G06F5/01
- IPC分类号: G06F5/01 ; G06F7/38 ; G06F7/52
摘要:
A scaling multiplier circuit in accordance with the invention includes a multiplier circuit, a carry calculation circuit, a logic circuit, and an adder circuit. The multiplier circuit produces a 16-bit product of two 8-bit input numbers. The 16-bit product has bits m(15:0). The carry calculation circuit produces a first carryout bit from a sum of a first number consisting of bits m(6:0), a second number consisting of bits m(14:8), and a third number consisting of bit m(7). The logic circuit produces intermediate carryout bits from a sum of bit m(7m), m(15), the first carryout bit, and a constant bit having a value of "1". The adder circuit produces the actual scaled product by summing the intermediate carryout bits and a fourth number consisting of bits m(15:8).
公开/授权文献
- US5478957A Preparation of 6.alpha., 9.alpha.-difluoro steroids 公开/授权日:1995-12-26
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