发明授权
US06174767B1 Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise
失效
8F2 DRAM单元的电容器和位线在同一电平上的制造方法，具有最小的位线耦合噪声
- 专利标题： Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise
- 专利标题（中）： 8F2 DRAM单元的电容器和位线在同一电平上的制造方法，具有最小的位线耦合噪声
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申请号： US09075370申请日： 1998-05-11
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公开(公告)号： US06174767B1公开(公告)日： 2001-01-16
- 发明人: Min-Hwa Chi
- 申请人： Min-Hwa Chi
- 主分类号： H01L218242
- IPC分类号： H01L218242
摘要：
A structure with bit lines and capacitors for a semiconductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxide layer, the conductive plugs being separated by a first dielectric material in a direction oriented transversely of the gate electrode stacks. Form a first interpolysilicon layer above the conductive plugs. Form bit-lines in the first interpolysilicon layer above the first dielectric material. Form a capacitor above a plug and between a pair of the bit-lines.
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