发明授权
- 专利标题: DRAM using oxide plug in bitline contacts during fabrication
- 专利标题(中): DRAM在制造期间使用位线触点中的氧化物塞
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申请号: US09414099申请日: 1999-10-07
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公开(公告)号: US06177695B1公开(公告)日: 2001-01-23
- 发明人: Erik S. Jeng
- 申请人: Erik S. Jeng
- 优先权: TW87121345 19981221
- 主分类号: H01L27108
- IPC分类号: H01L27108
摘要:
The conventional capacitor-under-bitline (CUB) DRAM structure faces problems of high photoresist developing aspect ratio and step-height. The present invention discloses a DRAM with planar upper-plate structure and the upper-plate forms an opening broader than the bitline contacts at the top of the lower-plate neighboring the bitline contacts to isolate from the bitline contacts, and the step height at the interface between the peripheral circuit and cell arrays almost does not exist. Furthermore, conventional problems could be solved because of an oxide plug during producing bitline contacts and the thick oxide deposited on the peripheral circuit. A lightly doped polysilicon is deposited between the lower-plate and the silicon wafer substrate to avoid current leakage of the lower-plate.
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