发明授权
US06177826B1 Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate
失效
具有串联连接的PMOS晶体管的绝缘体上硅电路，每个具有连接体和栅极
- 专利标题： Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate
- 专利标题（中）： 具有串联连接的PMOS晶体管的绝缘体上硅电路，每个具有连接体和栅极
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申请号： US09053700申请日： 1998-04-02
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公开(公告)号： US06177826B1公开(公告)日： 2001-01-23
- 发明人: Koichiro Mashiko , Kimio Ueda , Yoshiki Wada
- 申请人： Koichiro Mashiko , Kimio Ueda , Yoshiki Wada
- 优先权： JP9-330637 19971201
- 主分类号： H03K190948
- IPC分类号： H03K190948
摘要：
A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.