发明授权
US06178518B1 Semiconductor memory system comprising synchronous DRAM and controller 失效
包括同步DRAM和控制器的半导体存储器系统

  • 专利标题: Semiconductor memory system comprising synchronous DRAM and controller
  • 专利标题(中): 包括同步DRAM和控制器的半导体存储器系统
  • 申请号: US09165692
    申请日: 1998-10-02
  • 公开(公告)号: US06178518B1
    公开(公告)日: 2001-01-23
  • 发明人: Haruki Toda
  • 申请人: Haruki Toda
  • 优先权: JP9-269779 19971002
  • 主分类号: G06F104
  • IPC分类号: G06F104
Semiconductor memory system comprising synchronous DRAM and controller
摘要:
A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.
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