发明授权
US06183122B2 Multiplier sign extension 失效
乘数符号扩展

  • 专利标题: Multiplier sign extension
  • 专利标题(中): 乘数符号扩展
  • 申请号: US08923132
    申请日: 1997-09-04
  • 公开(公告)号: US06183122B2
    公开(公告)日: 2001-02-06
  • 发明人: Edwin De Angel
  • 申请人: Edwin De Angel
  • 主分类号: G06F750
  • IPC分类号: G06F750
Multiplier sign extension
摘要:
A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data to form a plurality of factored multiplicands. The sum of the factored multiplicands is augmented by two additional bits for all but the last of the factored multiplicands and by a logic 1 bit. The two additional bits are a logic 1 followed by the inverse of the sign bit of the factored multiplicand and are placed in the next two significant bit positions after the sign bit of the factored multiplicand, and the logic 1 is in the position occupied by the sign bit of the factored multiplicands which has the least significant bit position of all of the sign bits of the factored multiplicands.
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